A Low Latency, Low-Power LDPC Decoder Design

A low latency, low power LDPC decoder design is presented in the paper. Partial-parallel check node processors are designed to reduce the decoding latency with moderate complexity; the parity check matrices of the LDPC codes are column-wise reordered to facilitate the parallel processing. Meanwhile, an efficient early stopping algorithm is proposed to stop the ‘undecodable’ words so that at least more than half power consumption is saved for low to median SNR region. The proposed LDPC decoder architecture has been implemented for IEEE 802.11n/ac LDPC codes on Xilinx Virtex6 device with a maximum throughput of more than 600 Mbps.